1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices. For example, at least some example embodiments of the present invention provide semiconductor memory devices operating with a latency dependent on a frequency of an external clock signal and methods for generating a column enable signal thereof.
2. Description of The Conventional Art
A conventional semiconductor memory device may operate with a latency dependent on an external clock signal frequency. However, even though the latency may vary, a row enable signal may be activated constantly and may maintain the activation state during a time period before deactivation. On the other hand, a column enable signal may be delayed for a clock cycle corresponding to the latency prior to activation. For example, even though the latency may vary, an activation time of the row enable signal may be the same or substantially the same, while an activation time of the column enable signal may vary.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. The conventional semiconductor memory device of FIG. 1 may include a memory cell array 100, a command decoder 10, a mode setting circuit 12, a clock buffer 14, a column enable signal generator 16, a row enable signal generator 18, a column decoder 20 and a row decoder 22. In FIG. 1, “MC” denotes a representative memory cell, “BL” denotes a representative bit line and “WL” denotes a representative word line.
The command decoder 10 may decode a command signal COM applied from an external source to generate a read command RD and a mode setting command MRS. The mode setting circuit 12 may receive a code CODE applied from an external source to generate a burst length signal BLS and a latency signal LA in response to the mode setting command MRS. The clock buffer 14 may buffer an external clock signal CLK to generate a buffered clock signal PCLK. The column enable signal generator 16 may receive the read command RD, the burst length signal BLS, the latency signal LA, and the buffered clock signal PCLK, and may generate a latency control signal (not shown). The latency control signal may be activated after being delayed for a clock cycle corresponding to the latency signal LA after the read command RD is applied. The column enable signal generator 16 may deactivate the latency control signal after being activated for a clock cycle corresponding to the burst length signal BLS and may generate the buffered clock signal PCLK as a column enable signal PCSLE in response to the latency control signal.
The row enable signal generator 18 may generate a row enable signal PWL, which may be activated after a time period, and may be deactivated after being activated for a time period. The row enable signal generator 18 may generate the row enable signal PWL in response to the read command RD. The column decoder 20 may decode a column address CA to activate one of n column selecting signals CSL1 to CSLn in response to the column enable signal PCSLE. The row decoder 22 may decode a row address RA to activate one of m word line selecting signals WL1 to WLm in response to the row enable signal PWL.
FIG. 2 is a block diagram illustrating the column enable signal generator of the conventional semiconductor memory device of FIG. 1. The column enable signal generator of FIG. 2 may include a latency control signal generator 30 and an enable signal generator 32.
The latency control signal generator 30 may activate a latency control signal lat after being delayed in response to the buffered clock signal PCLK and after the read command RD is generated. The delay may comprise a clock cycle corresponding to the latency signal LA. The latency control signal generator 30 may deactivate the latency control signal lat using the buffered clock signal PCLK after maintaining the activation state for a clock cycle corresponding to the burst length signal BLS. The enable signal generator 32 may generate the buffered clock signal PCLK as the column enable signal PCSLE in response to the latency control signal lat.
FIG. 3a is a timing diagram illustrating an example operation of the semiconductor memory device of FIG. 1. In the example shown in FIG. 3A, the latency signal LA is set to 2, and the burst length signal BLS is set to 4. A latency signal LA set to 2 indicates that data may be read 2 clock cycles after the read command RD is generated. The burst length signal BLS set to 4 indicates that 4 data may be output sequentially through one data output pin.
Referring to FIG. 3a, when the read command RD is applied, the row enable signal PWL may be activated a time T1 after (and in response to) the read command RD and may be deactivated after a time T2. The row decoder 22 may decode the row address RA to activate one word line selecting signal WL in response to the row enable signal PWL. The latency control signal generator 30 may generate the latency control signal lat after the read command RD is applied, and the latency control signal lat may be active being delayed for 2 clock cycles corresponding to the latency signal 1a. The latency control signal lat may be deactivated after maintaining the activation state for 4 clock cycles corresponding to the burst length signal BLS. The enable signal generator 32 may generate the buffered clock signal PCLK as the column enable signal PCSLE in response to the latency control signal lat. Thus, 4 column enable signals PCSLE may be generated sequentially. The column decoder 20 may decode the column address CA to activate a first column selecting signal CSL1 in response to the column enable signal PCSLE. Second to fourth column selecting signals CSL2 to CSL4 may be activated sequentially. Although not shown, the row address RA and/or a first column address CA may be applied concurrently with the command signal CMD. The row address RA may be applied to the row decoder 22, the first column address CA may be applied to an internal address generator (not shown), and the internal address generator (not shown) may sequentially generate 4 column addresses corresponding to the burst length signal BLS.
FIG. 3B is a timing diagram illustrating an example operation of the semiconductor memory device of FIG. 1 in which a frequency of the clock signal CLK is higher than the frequency of the clock signal CLK of FIG. 3A, the latency signal LA is set to 3 and the burst length signal BLS is set to 4.
In FIG. 3B, the row enable signal PWL may be generated in the same or substantially the same manner as in FIG. 3A. The clock buffer 14 may buffer the clock signal CLK to generate the buffered clock signal PCLK. The row decoder 22 may decode the row address RA to activate one word line selecting signal WL in response to the row enable signal PWL. The latency control signal generator 30 may generate the latency control signal lat after the read command RD is applied. The latency control signal lat may be activated after being delayed for 3 clock cycles corresponding to the latency signal LA. The latency control signal lat may be deactivated after being maintained in an activation state for 4 clock cycles corresponding to the burst length signal BLS. The enable signal generator 32 may generate the buffered clock signal PCLK as the column enable signal PCSLE in response to the latency control signal lat. Thus, 4 column enable signals PCSLE may be generated sequentially. The column decoder 20 may decode the column address CA to sequentially activate first to fourth column selecting signals CSL1 to CSL4 in response to the column enable signal PCSLE. Four column addresses CA may be generated by the internal address generator (not shown).
As shown in FIGS. 3A and 3B, the latency changes as the frequency of the clock signal varies, while the row enable signal PWL may be generated at the same time point. However, as the latency varies, a time at which the latency control signal lat is generated may vary. Thus, a time period spanning from the generation of the word line enable signal WL to the generation of the first column selecting signal CSL1 may be t1 in FIG. 3A and t2 in FIG. 3B. Time periods t1 and t2 may be different.
The time period from generation of the word line enable signal WL to generation of the first column selecting signal CSL1 may vary as the latency varies, depend on variations in process, voltage and/or temperature. As a result, if data of the bit line pair is not sufficiently amplified, the first column selecting signal CSL1 may be generated, and the data of the bit line may be read, which may result in data read errors.